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general description the MAX12557 is a dual 3.3v, 14-bit analog-to-digital converter (adc) featuring fully differential wideband track-and-hold (t/h) inputs, driving internal quantizers. the MAX12557 is optimized for low power, small size, and high dynamic performance in intermediate frequen- cy (if) and baseband sampling applications. this dual adc operates from a single 3.3v supply, consuming only 610mw while delivering a typical 72.5db signal-to- noise ratio (snr) performance at a 175mhz input fre- quency. the t/h input stages accept single-ended or differential inputs up to 400mhz. in addition to low oper- ating power, the MAX12557 features a 166? power- down mode to conserve power during idle periods. a flexible reference structure allows the MAX12557 to use the internal 2.048v bandgap reference or accept an externally applied reference and allows the refer- ence to be shared between the two adcs. the refer- ence structure allows the full-scale analog input range to be adjusted from ?.35v to ?.15v. the MAX12557 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. the MAX12557 supports either a single-ended or differ- ential input clock. user-selectable divide-by-two (div2) and divide-by-four (div4) modes allow for design flexibil- ity and help eliminate the negative effects of clock jitter. wide variations in the clock duty cycle are compensated with the adc? internal duty-cycle equalizer (dce). the MAX12557 features two parallel, 14-bit-wide, cmos-compatible outputs. the digital output format is pin-selectable to be either two? complement or gray code. a separate power-supply input for the digital out- puts accepts a 1.7v to 3.6v voltage for flexible interfac- ing with various logic levels. the MAX12557 is available in a 10mm x 10mm x 0.8mm, 68-pin thin qfn package with exposed paddle (ep), and is specified for the extended (-40 c to +85 c) temperature range. for a 12-bit, pin-compatible version of this adc, refer to the max12527 data sheet. applications if and baseband communication receivers cellular, lmds, point-to-point microwave, mmds, hfc, wlan i/q receivers ultrasound and medical imaging portable instrumentation digital set-top boxes low-power data acquisition features ? direct if sampling up to 400mhz ? excellent dynamic performance 74.1db/72.5db snr at f in = 70mhz/175mhz 83.4dbc/79.5dbc sfdr at f in = 70mhz/175mhz ? 3.3v low-power operation 637mw (differential clock mode) 610mw (single-ended clock mode) ? fully differential or single-ended analog input ? adjustable differential analog input voltage ? 750mhz input bandwidth ? adjustable, internal or external, shared reference ? differential or single-ended clock ? accepts 25% to 75% clock duty cycle ? user-selectable div2 and div4 clock modes ? power-down mode ? cmos outputs in two? complement or gray code ? out-of-range and data-valid indicators ? small, 68-pin thin qfn package ? 12-bit compatible version available (max12527) ? evaluation kit available (order MAX12557 ev kit) MAX12557 dual, 65msps, 14-bit, if/baseband adc ________________________________________________________________ maxim integrated products 1 ordering information 19-3544; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX12557etk -40 c to +85 c 68 thin qfn-ep* (10mm x 10mm x 0.8mm) * ep = exposed paddle. part sampling rate ( msps) resolution (bits) MAX12557 65 14 max12527 65 12 selector guide pin configuration appears at end of data sheet.
MAX12557 dual, 65msps, 14-bit, if/baseband adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ................................................................-0.3v to +3.6v ov dd to gnd............-0.3v to the lower of (v dd + 0.3v) and +3.6v inap, inan to gnd ...-0.3v to the lower of (v dd + 0.3v) and +3.6v inbp, inbn to gnd ...-0.3v to the lower of (v dd + 0.3v) and +3.6v clkp, clkn to gnd ........................-0.3v to the lower of (v dd + 0.3v) and +3.6v refin, refout to gnd ..................-0.3v to the lower of (v dd + 0.3v) and +3.6v refap, refan, coma to gnd ......-0.3v to the lower of (v dd + 0.3v) and +3.6v refbp, refbn, comb to gnd ......-0.3v to the lower of (v dd + 0.3v) and +3.6v diffclk/ seclk , g/ t , pd, shref, div2, div4 to gnd .........-0.3v to the lower of (v dd + 0.3v) and +3.6v d0a?13a, d0b?13b, dav, dora, dorb to gnd..............................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 68-pin thin qfn 10mm x 10mm x 0.8mm (derate 70mw/? above +70?) ....................................4000mw operating temperature range................................-40? to +85? junction temperature ...........................................................+150? storage temperature range .................................-65? to +150? lead temperature (soldering 10s).......................................+300? parameter symbol conditions min typ max units dc accuracy resolution 14 bits integral nonlinearity inl f in = 3mhz ?.1 lsb differential nonlinearity dnl f in = 3mhz, no missing codes over temperature (note 2) -1.0 ?.6 +1.3 lsb offset error ?.1 0.9 %fsr gain error ?.5 ?.0 %fsr analog input (inap, inan, inbp, inbn) differential input voltage range v diff differential or single-ended inputs ?.024 v common-mode input voltage v dd / 2 v analog input resistance r in each input, figure 3 3.4 k ? c par fixed capacitance to ground, each input, figure 3 2 analog input capacitance c sample switched capacitance, each input, figure 3 4.5 pf conversion rate maximum clock frequency f clk 65 mhz minimum clock frequency 5 mhz data latency figure 5 8 clock cycles dynamic characteristics (differential inputs) small-signal noise floor ssnf input at -35dbfs 74.5 76 dbfs f in = 3mhz at -0.5dbfs 72.5 75 f in = 32.5mhz at -0.5dbfs 74.5 f in = 70mhz at -0.5dbfs 74.1 signal-to-noise ratio snr f in = 175mhz at -0.5dbfs 70.4 72.5 db
MAX12557 dual, 65msps, 14-bit, if/baseband adc _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units f in = 3mhz at -0.5dbfs (note 3) 71.8 74.4 f in = 32.5mhz at -0.5dbfs 73.10 f in = 70mhz at -0.5dbfs 73.4 signal-to-noise plus distortion sinad f in = 175mhz at -0.5dbfs 71.5 db f in = 3mhz at -0.5dbfs (note 3) 75.5 86.6 f in = 32.5mhz at -0.5dbfs 82.8 f in = 70mhz at -0.5dbfs 83.4 spurious-free dynamic range sfdr f in = 175mhz at -0.5dbfs 79.5 dbc f in = 3mhz at -0.5dbfs (note 3) -84.5 -74.5 f in = 32.5mhz at -0.5dbfs -80.7 f in = 70mhz at -0.5dbfs -81.7 total harmonic distortion thd f in = 175mhz at -0.5dbfs -78.3 dbc f in = 3mhz at -0.5dbfs -89.5 f in = 32.5mhz at -0.5dbfs -84.2 f in = 70mhz at -0.5dbfs -84.7 second harmonic hd2 f in = 175mhz at -0.5dbfs -79.5 dbc f in = 3mhz at -0.5dbfs -93 f in = 32.5mhz at -0.5dbfs -85.5 f in = 70mhz at -0.5dbfs -86.5 third harmonic hd3 f in = 175mhz at -0.5dbfs -87.2 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs -88 two-tone intermodulation distortion (note 2) ttimd f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs -82.4 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs -91.5 3rd-order intermodulation distortion im3 f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs -87.6 dbc f in1 = 68.5mhz at -7dbfs f in2 = 71.5mhz at -7dbfs 89 two-tone spurious-free dynamic range sfdr tt f in1 = 172.5mhz at -7dbfs f in2 = 177.5mhz at -7dbfs 82.4 dbc full-power bandwidth fpbw input at -0.2dbfs, -3db rolloff 750 mhz aperture delay t ad figure 5 1.2 ns aperture jitter t aj <0.15 ps rms output noise n out inap = inan = coma inbp = inbn = comb 1.02 lsb rms
MAX12557 dual, 65msps, 14-bit, if/baseband adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units overdrive recovery time ?0% beyond full scale 1 clock cycle interchannel characteristics f ina or f inb = 70mhz at -0.5dbfs 90 crosstalk rejection f ina or f inb = 175mhz at -0.5dbfs 85 db gain matching ?.01 ?.1 db offset matching ?.01 %fsr internal reference (refout) refout output voltage v refout 2.000 2.048 2.080 v refout load regulation -1ma < i refout < +1ma 35 mv/ma refout temperature coefficient tc ref ?0 ppm/? short to v dd ?inking 0.24 refout short-circuit current short to gndsourcing 2.1 ma buffered reference mode (refin is driven by refout or an external 2.048v single-ended reference source; v refap /v refan /v coma and v refbp /v refbn /v comb are generated internally) refin input voltage v refin 2.048 v refin input resistance r refin >50 m ? com_ output voltage v coma v comb v dd / 2 1.60 1.65 1.70 v ref_p output voltage v refap v refbp v dd / 2 + (v refin x 3/8) 2.418 v ref_n output voltage v refan v refbn v dd / 2 - (v refin x 3/8) 0.882 v differential reference voltage v refa v refb v refa = v refap - v refan v refb = v refbp - v refbn 1.460 1.536 1.580 v differential reference temperature coefficient tc ref ?5 ppm/? unbuffered external reference (refin = gnd, v refap /v refan /v coma and v refbp /v refbn /v comb are applied externally, v coma = v comb = v dd / 2) ref_p input voltage v refap v refbp v ref_p - v com +0.768 v ref_n input voltage v refan v refbn v ref_n - v com -0.768 v com_ input voltage v com v dd / 2 1.65 v differential reference voltage v refa v refb v ref_ = v ref_p - v ref_n = v refin x 3/4 1.536 v
MAX12557 dual, 65msps, 14-bit, if/baseband adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units ref_p sink current i refap i refbp v ref_p = 2.418v 1.2 ma ref_n source current i refan i refbn v ref_n = 0.882v 0.85 ma com_ sink current i coma i comb v com_ = 1.65v 0.85 ma ref_p, ref_n capacitance c ref_p , c ref_n 13 pf com_ capacitance c com_ 6pf clock inputs (clkp, clkn) single-ended input high threshold v ih diffclk/ seclk = gnd, clkn = gnd 0.8 x v dd v single-ended input low threshold v il diffclk/ seclk = gnd, clkn = gnd 0.2 x v dd v minimum differential clock input voltage swing diffclk/ seclk = ov dd 0.2 v p-p differential input common-mode voltage diffclk/ seclk = ov dd v dd / 2 v clk_ input resistance r clk each input, figure 4 5 k ? clk_ input capacitance c clk 2pf digital inputs (diffclk/ seclk , g/ t , pd, div2, div4) input high threshold v ih 0.8 x ov dd v input low threshold v il 0.2 x ov dd v ov dd applied to input ? input leakage current input connected to ground ? ? digital input capacitance c din 5pf digital outputs (d0a?13a, d0b?13b, dora, dorb, dav) d0a?13a, d0b?13b, dora, dorb: i sink = 200? 0.2 output-voltage low v ol dav: i sink = 600? 0.2 v d0a?13a, d0b?13b, dora, dorb: i source = 200? ov dd - 0.2 output-voltage high v oh dav: i source = 600? ov dd - 0.2 v ov dd applied to input ? tri-state leakage current (note 3) i leak input connected to ground ? ?
MAX12557 dual, 65msps, 14-bit, if/baseband adc 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units d 0ad 13a, d o ra, d 0bd 13b and d o rb tr i - s tate o utp ut c ap aci tance ( n ote 3) c out 3pf dav tri-state output capacitance (note 3) c dav 6pf power requirements analog supply voltage v dd 3.15 3.30 3.60 v digital output supply voltage ov dd 1.70 2.0 v dd v normal operating mode f in = 175mhz at -0.5dbfs, single-ended clock (diffclk/ seclk = gnd) 185 normal operating mode f in = 175mhz at -0.5dbfs differential clock (diffclk/ seclk = ov dd ) 193 210 analog supply current i vdd power-down mode (pd = ov dd ) clock idle 0.05 ma normal operating mode f in = 175mhz at -0.5dbfs single-ended clock (diffclk/ seclk = gnd) 610 normal operating mode f in = 175mhz at -0.5dbfs differential clock (diffclk/ seclk = ov dd ) 637 693 analog power dissipation p vdd power-down mode (pd = ov dd ) clock idle 0.165 mw normal operating mode f in = 175mhz at -0.5dbfs 21.3 digital output supply current i ovdd power-down mode (pd = ov dd ) clock idle 0.001 ma
MAX12557 dual, 65msps, 14-bit, if/baseband adc _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference), c l 10pf at digital outputs, v in = -0.5dbfs (differen- tial), diffclk/ seclk = ov dd , pd = gnd, shref = gnd, div2 = gnd, div4 = gnd, g/ t = gnd, f clk = 65mhz, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units timing characteristics (figure 5) clock pulse-width high t ch 7.7 ns clock pulse-width low t cl 7.7 ns data-valid delay t dav 5.4 ns data setup time before rising edge of dav t setup (note 6) 7.0 ns data hold time after rising edge of dav t hold (note 6) 7.0 ns wake-up time from power-down t wake v refin = 2.048v 10 ms note 1: specifications +25? guaranteed by production test, <+25? guaranteed by design and characterization. note 2: guaranteed by design and characterization. device tested for performance during product test. note 3: specification guaranteed by production test for +25?. note 4: two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input power of both input tones. note 5: during power-down, d0a?13a, d0b?13b, dora, dorb, and dav are high impedance. note 6: guaranteed by design and characterization. t ypical operating characteristics (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference mode), c l 5pf at digital outputs, v in = -0.5dbfs, diffclk/ seclk = ov dd , pd = gnd, g/ t = gnd, f clk = 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.) fft plot (32,768-point data record) MAX12557 toc01 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 hd3 f clk = 65mhz f in = 3.00125mhz a in = -0.48dbfs snr = 74.45db sinad = 74.33db thd = -90.06dbc sfdr = 92.47dbc hd2 -10 -30 -50 -70 -90 -110 30 25 15 20 10 5 0 fft plot (32,768-point data record) MAX12557 toc02 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 hd3 f clk = 65.00352mhz f in = 32.40058mhz a in = -0.424dbfs snr = 74.77db sinad = 74.62db thd = -87.22dbc sfdr = 91.88dbc hd2 -10 -30 -50 -70 -90 -110 30 25 15 20 10 5 0 fft plot (32,768-point data record) MAX12557 toc03 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 f clk = 65.00352mhz f in = 70.00852mhz a in = -0.498dbfs snr = 74.41db sinad = 74.00db thd = -84.50dbc sfdr = 86.25dbc hd2 -10 -30 -50 -70 -90 -110 hd3 30 25 15 20 10 5 0
MAX12557 dual, 65msps, 14-bit, if/baseband adc 8 _______________________________________________________________________________________ -2.0 -1.0 -1.5 0 -0.5 0.5 1.0 1.5 2.0 0 4096 6144 2048 8192 10240 12288 14336 16384 integral nonlinearity vs. digital output code (4,194,304-point data record) MAX12557 toc07 digital output code inl (lsb) f in = 3.00123mhz -1.00 -0.50 -0.75 0 -0.25 0.25 0.50 0.75 1.00 0 4096 6144 2048 8192 10240 12288 14336 16384 differential nonlinearity vs. digital output code (4,194,304-point data record) MAX12557 toc08 digital output code dnl (lsb) f in = 3.00123mhz 40 50 45 60 55 65 70 75 80 0 100 150 50 200 250 300 350 400 snr, sinad vs. analog input frequency (f clk = 65.00352mhz, a in = -0.5dbfs) MAX12557 toc09 f in (mhz) snr, sinad (db) snr sinad 50 60 55 75 70 65 90 85 80 95 0 150 200 50 100 250 300 350 400 -thd, sfdr vs. analog input frequency (f clk = 65.00352mhz, a in = -0.5dbfs) MAX12557 toc10 f in (mhz) -thd, sfdr (dbc) sfdr -thd 20 40 30 60 50 70 80 -55 -45 -40 -35 -50 -30 -25 -20 -15 -10 -5 0 MAX12557 toc11 a in (dbfs) snr, sinad (db) snr, sinad vs. analog input amplitude (f clk = 65.00352mhz, f in = 70mhz) sinad snr 35 55 45 75 65 85 95 -55 -45 -40 -35 -50 -30 -25 -20 -15 -10 -5 0 MAX12557 toc12 a in (dbfs) -thd, sfdr (dbc) -thd, sfdr vs. analog input amplitude (f clk = 65.00352mhz, f in = 70mhz) -thd sfdr fft plot (32,768-point data record) MAX12557 toc04 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 f clk = 65.00352mhz f in = 174.98857mhz a in = -0.476dbfs snr = 72.37db sinad = 70.48db thd = -75.62dbc sfdr = 76.37dbc hd2 -10 -30 -50 -70 -90 -110 hd3 30 25 15 20 10 5 0 two-tone imd plot (16,384-point data record) MAX12557 toc05 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 f clk = 65.00352mhz f in1 = 68.49987mhz a in1 = -6.97dbfs f in2 = 71.49930db a in2 = -6.99dbfs im3 = -91.54dbc imd = -87.97dbc -10 -30 -50 -70 -90 -110 hd3 2f in2 + f in1 2f in1 + f in2 f in2 f in1 30 25 15 20 10 5 0 two-tone imd plot (16,384-point data record) MAX12557 toc06 analog input frequency (mhz) amplitude (dbfs) -100 -80 -60 -40 -20 0 -120 f clk = 65.00352mhz f in1 = 172.49995mhz a in1 = -6.95dbfs f in2 = 177.49900688mhz a in2 = -6.97dbfs im3 = -87.61dbc imd = -82.37dbc -10 -30 -50 -70 -90 -110 hd3 f in1 + f in2 f in1 f in2 hd2 30 25 15 20 10 5 0 t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference mode), c l 5pf at digital outputs, v in = -0.5dbfs, diffclk/ seclk = ov dd , pd = gnd, g/ t = gnd, f clk = 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12557 dual, 65msps, 14-bit, if/baseband adc _______________________________________________________________________________________ 9 20 40 30 60 50 70 80 -55 -45 -40 -35 -50 -30 -25 -20 -15 -10 -5 0 MAX12557 toc13 a in (dbfs) snr, sinad (db) snr, sinad vs. analog input amplitude (f clk = 65.00352mhz, f in = 175mhz) sinad snr 35 55 45 75 65 85 95 -55 -45 -40 -35 -50 -30 -25 -20 -15 -10 -5 0 MAX12557 toc14 a in (dbfs) -thd, sfdr (dbc) -thd, sfdr vs. analog input amplitude (f clk = 65.00352mhz, f in = 175mhz) -thd sfdr 60 64 68 72 76 80 20 35 40 25 30 45 50 55 60 65 snr, sinad vs. clock speed (f in = 70mhz, a in = -0.5dbfs) MAX12557 toc15 f clk (mhz) snr, sinad (db) snr sinad 60 70 75 80 85 90 20 35 40 25 30 45 50 55 60 65 -thd, sfdr vs. clock speed (f in = 70mhz, a in = -0.5dbfs) MAX12557 toc16 f clk (mhz) -thd, sfdr (dbc) sfdr -thd 65 60 64 68 72 76 80 20 35 40 25 30 45 50 55 60 65 snr, sinad vs. clock speed (f in = 175mhz, a in = -0.5dbfs) MAX12557 toc17 f clk (mhz) snr, sinad (db) snr sinad 60 70 75 80 85 90 20 35 40 25 30 45 50 55 60 65 -thd, sfdr vs. clock speed (f in = 175mhz, a in = -0.5dbfs) MAX12557 toc18 f clk (mhz) -thd, sfdr (dbc) -thd 65 sfdr 60 64 72 68 76 80 3.0 3.2 3.1 3.3 3.4 3.5 3.6 snr, sinad vs. analog supply voltage (f clk = 65.00352mhz, f in = 70mhz) MAX12557 toc19 v dd (v) snr, sinad (db) snr sinad 60 70 65 80 75 90 85 95 3.0 3.2 3.3 3.1 3.4 3.5 3.6 MAX12557 toc20 v dd (v) -thd, sfdr (dbc) -thd, sfdr vs. analog supply voltage (f clk = 65.00352mhz, f in = 70mhz) sfdr -thd 60 63 69 66 72 75 3.0 3.2 3.1 3.3 3.4 3.5 3.6 snr, sinad vs. analog supply voltage (f clk = 65.00352mhz, f in = 175mhz) MAX12557 toc21 v dd (v) snr, sinad (db) snr sinad t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference mode), c l 5pf at digital outputs, v in = -0.5dbfs, diffclk/ seclk = ov dd , pd = gnd, g/ t = gnd, f clk = 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12557 dual, 65msps, 14-bit, if/baseband adc 10 ______________________________________________________________________________________ 60 65 75 70 80 85 3.0 3.2 3.1 3.3 3.4 3.5 3.6 -thd, sfdr vs. analog supply voltage (f clk = 65.00352mhz, f in = 175mhz) MAX12557 toc22 v dd (v) -thd, sfdr (dbc) sfdr -thd 60 64 72 68 76 80 1.5 2.1 1.8 2.4 2.7 3.0 3.3 snr, sinad vs. digital supply voltage (f clk = 65.00352mhz, f in = 70mhz) MAX12557 toc23 ov dd (v) snr, sinad (db) snr sinad 3.6 60 70 65 80 75 90 85 95 1.5 2.1 2.4 1.8 2.7 3.0 3.3 3.6 MAX12557 toc24 ov dd (v) -thd, sfdr (dbc) -thd, sfdr vs. digital supply voltage (f clk = 65.00352mhz, f in = 70mhz) sfdr -thd 60 63 69 66 72 75 1.5 2.1 1.8 2.4 2.7 3.0 3.3 snr, sinad vs. digital supply voltage (f clk = 65.00352mhz, f in = 175mhz) MAX12557 toc25 ov dd (v) snr, sinad (db) snr sinad 3.6 60 64 72 68 76 80 1.5 2.1 1.8 2.4 2.7 3.0 3.3 -thd, sfdr vs. digital supply voltage (f clk = 65.00352mhz, f in = 175mhz) MAX12557 toc26 ov dd (v) -thd, sfdr (dbc) sfdr -thd 3.6 0 200 100 500 400 300 800 700 600 900 3.0 3.2 3.1 3.3 3.4 3.5 3.6 p diss , i vdd (analog) vs. analog supply voltage (f clk = 65.00352mhz, f in = 175mhz) MAX12557 toc27 v dd (v) p diss , i vdd (mw, ma) p diss (analog) i vdd 0 20 10 40 30 70 60 50 80 1.5 2.1 1.8 2.4 2.7 3.0 3.3 3.6 MAX12557 toc28 ov dd (v) p diss , i ovdd (digital) vs. digital supply voltage (f clk = 65.00352mhz, f in = 175mhz) p diss , i ovdd (mw, ma) p diss (digital) c l 5pf i ovdd 60 64 62 68 66 70 72 25 45 35 55 65 75 snr, sinad vs. clock duty cycle (f in = 70mhz, a in = -0.5dbfs) MAX12557 toc29 clock duty cycle (%) snr, sinad (db) single-ended clock drive snr sinad 60 70 65 80 75 85 90 25 45 35 55 65 75 -thd, sfdr vs. clock duty cycle (f in = 70mhz, a in = -0.5dbfs) MAX12557 toc30 clock duty cycle (%) -thd, sfdr (dbc) single-ended clock drive sfdr -thd t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference mode), c l 5pf at digital outputs, v in = -0.5dbfs, diffclk/ seclk = ov dd , pd = gnd, g/ t = gnd, f clk = 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 11 60 66 64 62 72 70 68 74 76 -40 10 -15 35 60 85 snr, sinad vs. temperature (f in = 175mhz, a in = -0.5dbfs) MAX12557 toc31 temperature ( c) snr, sinad (db) snr sinad 60 70 65 80 75 85 90 -40 10 -15 35 60 85 -thd, sfdr vs. temperature (f in = 175mhz, a in = -0.5dbfs) MAX12557 toc32 temperature ( c) -thd, sfdr (dbc) sfdr -thd -3 -1 -2 1 0 2 3 -40 10 -15 35 60 85 gain error vs. temperature MAX12557 toc33 temperature ( c) gain error (%fsr) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -40 -15 10 35 60 85 offset error vs. temperature MAX12557 toc34 temperature ( c) offset error (%fsr) t ypical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.0v, gnd = 0, refin = refout (internal reference mode), c l 5pf at digital outputs, v in = -0.5dbfs, diffclk/ seclk = ov dd , pd = gnd, g/ t = gnd, f clk = 65mhz (50% duty cycle), t a = +25?, unless otherwise noted.)
MAX12557 dual, 65msps, 14-bit, if/baseband adc 12 ______________________________________________________________________________________ pin name function 1, 4, 5, 9, 13, 14, 17 gnd converter ground. connect all ground pins and the exposed paddle (ep) together. 2 inap channel a positive analog input 3 inan channel a negative analog input 6 coma channel a common-mode voltage i/o. bypass coma to gnd with a 0.1? capacitor. 7 refap channel a positive reference i/o. channel a conversion range is ?/3 x (v refap - v refan ). bypass refap with a 0.1? capacitor to gnd. connect a 10? and a 1? bypass capacitor between refap and refan. place the 1? refap-to-refan capacitor as close to the device as possible on the same side of the pc board. 8 refan channel a negative reference i/o. channel a conversion range is ?/3 x (v refap - v refan ). bypass refan with a 0.1? capacitor to gnd. connect a 10? and a 1? bypass capacitor between refap and refan. place the 1? refap-to-refan capacitor as close to the device as possible on the same side of the pc board. 10 refbn channel b negative reference i/o. channel b conversion range is ?/3 x (v refbp - v refbn ). bypass refbn with a 0.1? capacitor to gnd. connect a 10? and a 1? bypass capacitor between refbp and refbn. place the 1? refbp-to-refbn capacitor as close to the device as possible on the same side of the pc board. 11 refbp channel b positive reference i/o. channel b conversion range is ?/3 x (v refbp - v refbn ). bypass refbp with a 0.1? capacitor to gnd. connect a 10? and a 1? bypass capacitor between refbp and refbn. place the 1? refbp-to-refbn capacitor as close to the device as possible on the same side of the pc board. 12 comb channel a common-mode voltage i/o. bypass comb to gnd with a 0.1? capacitor. 15 inbn channel b negative analog input 16 inbp channel b positive analog input 18 diffclk/ seclk differential/single-ended input clock drive. this input selects between single-ended or differential clock input drives. diffclk/ seclk = gnd: selects single-ended clock input drive. diffclk/ seclk = ov dd : selects differential clock input drive. 19 clkn negative clock input. in differential clock input mode (diffclk/ seclk = ov dd ), connect a differential clock signal between clkp and clkn. in single-ended clock mode (diffclk/ seclk = gnd), apply the clock signal to clkp and connect clkn to gnd. 20 clkp positive clock input. in differential clock input mode (diffclk/ seclk = ov dd ), connect a differential clock signal between clkp and clkn. in single-ended clock mode (diffclk/ seclk = gnd), apply the single-ended clock signal to clkp and connect clkn to gnd. 21 div2 divide-by-two clock-divider digital control input. see table 2 for details. 22 div4 divide-by-four clock-divider digital control input. see table 2 for details. 23?6, 61, 62, 63 v dd analog power input. connect v dd to a 3.15v to 3.60v power supply. bypass v dd to gnd with a parallel capacitor combination of 10? and 0.1?. connect all v dd pins to the same potential. 27, 43, 60 ov dd output-driver power input. connect ov dd to a 1.7v to v dd power supply. bypass ov dd to gnd with a parallel capacitor combination of 10? and 0.1?. pin description
MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 13 pin name function 28 d0b channel b cmos digital output, bit 0 (lsb) 29 d1b channel b cmos digital output, bit 1 30 d2b channel b cmos digital output, bit 2 31 d3b channel b cmos digital output, bit 3 32 d4b channel b cmos digital output, bit 4 33 d5b channel b cmos digital output, bit 5 34 d6b channel b cmos digital output, bit 6 35 d7b channel b cmos digital output, bit 7 36 d8b channel b cmos digital output, bit 8 37 d9b channel b cmos digital output, bit 9 38 d10b channel b cmos digital output, bit 10 39 d11b channel b cmos digital output, bit 11 40 d12b channel b cmos digital output, bit 12 41 d13b channel b cmos digital output, bit 13 (msb) 42 dorb channel b data out-of-range indicator. the dorb digital output indicates when the channel b analog input voltage is out of range. dorb = 1: digital outputs exceed full-scale range. dorb = 0: digital outputs are within full-scale range. 44 dav data-valid digital output. the rising edge of dav indicates that data is present on the digital outputs. the MAX12557 evaluation kit utilizes dav to latch data into any external back-end digital logic. 45 d0a channel a cmos digital output, bit 0 (lsb) 46 d1a channel a cmos digital output, bit 1 47 d2a channel a cmos digital output, bit 2 48 d3a channel a cmos digital output, bit 3 49 d4a channel a cmos digital output, bit 4 50 d5a channel a cmos digital output, bit 5 51 d6a channel a cmos digital output, bit 6 52 d7a channel a cmos digital output, bit 7 53 d8a channel a cmos digital output, bit 8 54 d9a channel a cmos digital output, bit 9 55 d10a channel a cmos digital output, bit 10 56 d11a channel a cmos digital output, bit 11 57 d12a channel a cmos digital output, bit 12 58 d13a channel a cmos digital output, bit 13 (msb) 59 dora channel a data out-of-range indicator. the dora digital output indicates when the channel a analog input voltage is out of range. dora = 1: digital outputs exceed full-scale range. dora = 0: digital outputs are within full-scale range. 64 g/ t output format select digital input. g/ t = gnd: two?-complement output format selected. g/ t = ov dd : gray-code output format selected. pin description (continued)
MAX12557 detailed description the MAX12557 uses a 10-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. from input to output the total latency is 8 clock cycles. each pipeline converter stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital out- put code is multiplied and passed along to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. figure 2 shows the MAX12557 functional diagram. dual, 65msps, 14-bit, if/baseband adc 14 ______________________________________________________________________________________ pin name function 65 pd power-down digital input. pd = gnd: adcs are fully operational. pd = ov dd : adcs are powered down. 66 shref shared reference digital input. shref = v dd : shared reference enabled. shref = gnd: shared reference disabled. when sharing the reference, externally connect refap and refbp together to ensure that v refap = v refbp . similarly, when sharing the reference, externally connect refan to refbn together to ensure that v refan = v refbn . 67 refout inter nal refer e nce v ol tag e o utp ut. the re fou t outp ut vol tag e i s 2. 048v and re fo u t can d el i ver 1m a. for internal reference operation, connect refout directly to refin or use a resistive divider from refout to set the voltage at refin. bypass refout to gnd with a 0.1? capacitor. for external reference operation, refout is not required and must be bypassed to gnd with a 0.1? capacitor. 68 refin single-ended reference analog input. for i nter nal r efer ence and b uffer ed exter nal r efer e nce op er ati on, ap p l y a 0. 7v to 2.3v d c r efer ence vol tag e to re fin . b y p a s s ref i n t o gn d w it h a 4 . 7 ? f c a p a c i t o r . w i thi n i ts sp eci fi ed op er ati ng vol tag e, re fin has a > 50m ? i np ut i m p ed a nce, and t he d i ffer enti al r efer ence vol tag e ( v r e f_ p - v r e f_ n ) i s g ener ated fr om re fin . for unb uffer ed exter nal r efer ence op er ati on, connect re fin to g n d . in thi s m od e, re f_p , re f_n , and c o m _ ar e hi g h- i m p ed ance i np uts that accep t the exter nal r efer ence vol tag es. ?p exposed paddle. ep is internally connected to gnd. externally connect ep to gnd to achieve specified dynamic performance. pin description (continued) MAX12557 + ? digital error correction flash adc x2 dac stage 2 in_p in_n stage 1 stage 9 stage 10 end of pipeline d0_ through d13_ figure 1. pipeline architecture?tage blocks
MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 15 inbp 14-bit pipeline adc digital error correction channel a reference system coma refan refap ov dd dav output drivers dora clock divider d ata format 14-bit pipeline adc digital error correction output drivers d ata format div2 div4 inbn d0b to d13b dorb channel b reference system comb refbn refbp inap inan clkp clkn duty-cycle equalizer clock clock power control and bias circuits pd v dd gnd clock refin internal reference generator refout shref diffclk/seclk d0a to d13a g/t MAX12557 t/h t/h figure 2. functional diagram
MAX12557 analog inputs and input track-and-hold (t/h) amplifier figure 3 displays a simplified functional diagram of the input t/h circuit. this input t/h circuit allows for high analog input frequencies of 175mhz and beyond and supports a v dd / 2 common-mode input voltage. the MAX12557 sampling clock controls the switched- capacitor input t/h architecture (figure 3) allowing the analog input signals to be stored as charge on the sampling capacitors. these switches are closed (track mode) when the sampling clock is high and open (hold mode) when the sampling clock is low (figure 4). the analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors. to avoid signal degradation, these capacitors must be charged to one-half lsb accuracy within one-half of a clock cycle. the analog input of the MAX12557 supports differential or single- ended input drive. for optimum performance with dif- ferential inputs, balance the input impedance of in_p and in_n and set the common-mode voltage to mid- supply (v dd / 2). the MAX12557 provides the optimum common-mode voltage of v dd / 2 through the com output when operating in internal reference mode and buffered external reference mode. this com output voltage can be used to bias the input network as shown in figures 9, 10, and 11. reference output an internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX12557. the power-down logic input (pd) enables and disables the reference circuit. refout has approxi- mately 17k ? to gnd when the MAX12557 is powered down. the reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12557 or when pd transitions from high to low. the internal bandgap reference produces a buffered reference voltage of 2.048v ?% at the refout pin with a ?0ppm/? temperature coefficient. connect an external 0.1? bypass capacitor from refout to gnd for stability. refout sources up to 1ma and sinks up to 0.1ma for external circuits with a 35mv/ma load regulation. short-circuit protection limits i refout to a 2.1ma source current when shorted to gnd and a 0.24ma sink current when shorted to v dd . similar to refout, refin should be bypassed with a 4.7? capacitor to gnd. reference configurations the MAX12557 full-scale analog input range is ?/3 x v ref with a v dd / 2 ?.5v common-mode input range. v ref is the voltage difference between refap (refbp) and refan (refbn). the MAX12557 provides three modes of reference operation. the voltage at refin (v refin ) selects the reference operation mode (table 1). connect refout to refin either with a direct short or through a resistive divider to enter internal reference mode. com_, ref_p, and ref_n are low-impedance outputs with v com_ = v dd / 2, v refp = v dd / 2 + 3/8 x v refin , and v ref_n = v dd / 2 - 3/8 x v refin . bypass ref_p, ref_n, and com_ each with a 0.1? capacitor dual, 65msps, 14-bit, if/baseband adc 16 ______________________________________________________________________________________ v refin reference mode 35% v refout to 100% v refout internal reference mode. refin is driven by refout either through a direct short or a resistive divider. v com_ = v dd / 2 v ref_p = v dd / 2 + 3/8 x v refin v ref_n = v dd / 2 - 3/8 x v refin 0.7v to 2.3v buffered external reference mode. an external 0.7v to 2.3v reference voltage is applied to refin. v com_ = v dd / 2 v ref_p = v dd / 2 + 3/8 x v refin v ref_n = v dd / 2 - 3/8 x v refin <0.5v u nb uffer ed e xter nal refer ence m od e. re f_p , re f_n , and c o m _ ar e d r i ven b y exter nal r efer ence sour ces. the ful l - scal e anal og i np ut r ang e i s ( v r e f _p - v r e f _n ) x 2/ 3. table 1. reference modes MAX12557 c par 2pf v dd bond wire inductance 1.5nh in_p sampling clock *the effective resistance of the switched sampling capacitors is: *c sample 4.5pf c par 2pf v dd bond wire inductance 1.5nh in_n *c sample 4.5pf r in = 1 f clk x c sample figure 3. internal t/h circuit
to gnd. bypass ref_p to ref_n with a 10? capacitor. bypass refin and refout to gnd with a 0.1? capac- itor. the refin input impedance is very large (>50m ? ). when driving refin through a resistive divider, use resistances 10k ? to avoid loading refout. buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12557? internal bandgap reference. in buffered external reference mode, apply a stable reference volt- age source between 0.7v to 2.3v at refin. pins com_, ref_p, and ref_n are low-impedance outputs with v com_ = v dd / 2, v ref_p = v dd / 2 + 3/8 x v refin , and v ref_n = v dd / 2 - 3/8 x v refin . bypass ref_p, ref_n, and com_ each with a 0.1? capacitor to gnd. bypass ref_p to ref_n with a 10? capacitor. connect refin to gnd to enter unbuffered external ref- erence mode. connecting refin to gnd deactivates the on-chip reference buffers for com_, ref_p, and ref_n. with their buffers deactivated, com_, ref_p, and ref_n become high-impedance inputs and must be driven with separate, external reference sources. drive v com_ to v dd / 2 ?%, and drive ref_p and ref_n so v com_ = (v ref_p_ + v ref_n_ ) / 2. the analog input range is ?v ref_p_ - v ref_n ) x 2/3. bypass ref_p, ref_n, and com_ each with a 0.1? capacitor to gnd. bypass ref_p to ref_n with a 10? capacitor. for all reference modes, bypass refout with a 0.1? and refin with a 4.7? capacitor to gnd. the MAX12557 also features a shared reference mode, in which the user can achieve better channel-to-chan- nel matching. when sharing the reference (shref = v dd ), externally connect refap and refbp together to ensure that v refap = v refbp . similarly, when sharing the reference, externally connect refan to refbn together to ensure that v refan = v refbn . connect shref to gnd to disable the shared refer- ence mode of the MAX12557. in this independent refer- ence mode, a better channel-to-channel isolation is achieved. for detailed circuit suggestions and how to drive the adc in buffered/unbuffered external reference mode, see the applications information section. clock duty-cycle equalizer the MAX12557 has an internal clock duty-cycle equaliz- er, which makes the converter insensitive to the duty cycle of the signal applied to clkp and clkn. the con- verters allow clock duty-cycle variations from 25% to 75% without negatively impacting the dynamic performance. the clock duty-cycle equalizer uses a delay-locked loop (dll) to create internal timing signals that are duty-cycle independent. due to this dll, the MAX12557 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. clock input and clock control lines the MAX12557 accepts both differential and single- ended clock inputs with a wide 25% to 75% input clock duty cycle. for single-ended clock input operation, connect diffclk/ seclk and clkn to gnd. apply an external single-ended clock signal to clkp. to reduce clock jitter, the external single-ended clock must have sharp falling edges. for differential clock input opera- tion, connect diffclk/ seclk to ov dd . apply an external differential clock signal to clkp and clkn. consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. clkp and clkn enter high impedance when the MAX12557 is powered down (figure 4). low clock jitter is required for the specified snr perfor- mance of the MAX12557. the analog inputs are sam- pled on the falling (rising) edge of clkp (clkn), requiring this edge to have the lowest possible jitter. jitter limits the maximum snr performance of any adc according to the following relationship: where f in represents the analog input frequency and t j is the total system clock jitter. clock jitter is especially critical for undersampling applications. for instance, assuming that clock jitter is the only noise source, to obtain the specified 72.5db of snr with an input fre- quency of 175mhz the system must have less than 0.21ps of clock jitter. however, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.14ps to obtain the speci- fied 72.5dbc of snr at 175mhz. clock-divider control inputs (div2, div4) the MAX12557 features three different modes of sam- pling/clock operation (see table 2). pulling both control lines low, the clock-divider function is disabled and the converters sample at full clock speed. pulling div4 low and div2 high enables the divide-by-two feature, which sets the sampling speed to one-half the selected clock frequency. in divide-by-four mode, the converter sam- pling speed is set to one-fourth the clock speed of the MAX12557. divide-by-four mode is achieved by applying a high level to div4 and a low level to div2. the option to snr ft in j log = ? ? ? ? ? ? 20 1 2 MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 17
MAX12557 select either one-half or one-fourth of the clock speed for sampling provides design flexibility, relaxes clock requirements, and can minimize clock jitter. system timing requirements figure 5 shows the timing relationship between the clock, analog inputs, dav indicator, dor_ indicators, and the resulting output data. the analog input is sam- pled on the falling (rising) edge of clkp (clkn) and the resulting data appears at the digital outputs 8 clock cycles later. the dav indicator is synchronized with the digital out- put and optimized for use in latching data into digital back-end circuitry. alternatively, digital back-end cir- cuitry can be latched with the rising edge of the con- version clock (clkp - clkn). data-valid output dav is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. the MAX12557 output data changes on the falling edge of dav, and dav rises once the output data is valid. the falling edge of dav is synchronized to have a 5.4ns delay from the falling edge of the input clock. output data at d0a/b?13a/b and dora/b are valid from 7ns before the rising edge of dav to 7ns after the rising edge of dav. dav enters high impedance when the MAX12557 is powered down (pd = ov dd ). dav enters its high- impedance state 10ns after the rising edge of pd and becomes active again 10ns after pd transitions low. dav is capable of sinking and sourcing 600? and has three times the driving capabilities of d0a/b?13a/b and dora/b. dav is typically used to latch the MAX12557 output data into an external digital back-end circuit. keep the capacitive load on dav as low as possi- ble (<15pf) to avoid large digital currents feeding back into the analog portion of the MAX12557, thereby degrading its dynamic performance. buffering dav dual, 65msps, 14-bit, if/baseband adc 18 ______________________________________________________________________________________ MAX12557 clkp clkn v dd gnd 10k ? 10k ? 10k ? 10k ? duty-cycle equalizer s 1h s 2h s 2l s 1l switches s 1_ and s 2_ are open during power-down making clkp and clkn high impedance. switches s 2_ are open in single-ended clock mode. figure 4. siimplified clock input circuit div4 div2 function 00 clock divider disabled f sample = f clk 01 divide-by-two clock divider f sample = f clk / 2 10 divide-by-four clock divider f sample = f clk / 4 11 not allowed table 2. clock-divider control inputs dav n n + 1 n +2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 t dav t setup t ad n - 1 n - 2 n - 3 t hold t cl t ch differential analog input (in_p?n_n) clkn clkp (v ref_p - v ref_n ) x 2/3 (v ref_n - v ref_p ) x 2/3 n + 4 d0_?13_ dor 8.0 clock-cycle data latency t setup t hold nn + 1 n + 2 n + 3 n + 5 n + 6 n + 7 n - 1 n - 2 n - 3 n + 9 n + 8 figure 5. system timing diagram
externally isolates it from heavy capacitive loads. refer to the MAX12557 ev kit schematic for recommendations of how to drive the dav signal through an external buffer. data out-of-range indicator the dora and dorb digital outputs indicate when the analog input voltage is out of range. when dor_ is high, the analog input is out of range. when dor_ is low, the analog input is within range. the valid differential input range is from (v ref_p - v ref_n ) x 2/3 to (v ref_n - v ref_p ) x 2/3. signals outside of this valid differential range cause dor_ to assert high as shown in table 1. dor is synchronized with dav and transitions along with the output data d13?0. there is an 8 clock-cycle latency in the dor function as is with the output data (figure 5). dor_ is high impedance when the MAX12557 is in power-down (pd = high). dor_ enters a high-impedance state within 10ns after the rising edge of pd and becomes active 10ns after pd? falling edge. digital output data and output format selection the MAX12557 provides two 14-bit, parallel, tri-state output buses. d0a/b?13a/b and dora/b update on the falling edge of dav and are valid on the rising edge of dav. the MAX12557 output data format is either gray code or two? complement depending on the logic input g/ t . with g/ t high, the output data format is gray code. with g/ t low, the output data format is set to two? com- plement. see figure 8 for a binary-to-gray and gray-to- binary code conversion example. the following equations, table 3, figure 6, and figure 7 define the relationship between the digital output and the analog input. gray code (g/ t = 1): v in_p - v in_n = 2/3 x (v ref_p - v ref_n ) x 2 x (code 10 - 8192) / 16,384 two? complement (g/ t = 0): v in_p - v in_n = 2/3 x (v ref_p - v ref_n ) x 2 x code 10 / 16,384 where code 10 is the decimal equivalent of the digital output code as shown in table 3. MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 19 gray-code output code (g/ t = 1) two?-complement output code (g/ t = 0) binary d13a?0a d13b?0b dor h exa d ecim a l equivalent of d13a?0a d13b?0b decimal equivalent of d13a?0a d13b?0b (code 10 ) binary d13a?0a d13b?0b dor hexadecimal equivalent of d13a?0a d13b?0b decimal equivalent of d13a?0a d13b?0b (code 10 ) v in_p - v in_n v ref_p = 2.418v v ref_n = 0.882v 10 0000 0000 0000 1 0x2000 +16,383 01 1111 1111 1111 1 0x1fff +8191 >+1.023875v (data out of range) 10 0000 0000 0000 0 0x2000 +16,383 01 1111 1111 1111 0 0x1fff +8191 +1.023875v 10 0000 0000 0001 0 0x2001 +16,382 01 1111 1111 1110 0 0x1ffe +8190 +1.023750v 11 0000 0000 0011 0 0x3003 +8194 00 0000 0000 0010 0 0x0002 +2 +0.000250v 11 0000 0000 0001 0 0x3001 +8193 00 0000 0000 0001 0 0x0001 +1 +0.000125v 11 0000 0000 0000 0 0x3000 +8192 00 0000 0000 0000 0 0x0000 0 +0.000000v 01 0000 0000 0000 0 0x1000 +8191 11 1111 1111 1111 0 0x3fff -1 -0.000125v 01 0000 0000 0001 0 0x1001 +8190 11 1111 1111 1110 0 0x3ffe -2 -0.000250v 00 0000 0000 0001 0 0x0001 +1 10 0000 0000 0001 0 0x2001 -8191 -1.023875v 00 0000 0000 0000 0 0x0000 0 10 0000 0000 0000 0 0x2000 -8192 -1.024000v 00 0000 0000 0000 1 0x0000 0 10 0000 0000 0000 1 0x2000 -8192 <-1.024000v (data out of range) table 3. output codes vs. input voltage
MAX12557 the digital outputs d0a/b?13a/b are high impedance when the MAX12557 is in power-down (pd = 1) mode. d0a/b?13a/b enter this state 10ns after the rising edge of pd and become active again 10ns after pd transitions low. keep the capacitive load on the MAX12557 digital out- puts d0a/b?13a/b as low as possible (<15pf) to avoid large digital currents feeding back into the ana- log portion of the MAX12557 and degrading its dynam- ic performance. adding external digital buffers on the digital outputs helps isolate the MAX12557 from heavy capacitive loads. to improve the dynamic performance of the MAX12557, add 220 ? resistors in series with the digital outputs close to the MAX12557. refer to the MAX12557 ev kit schematic for guidelines of how to drive the digital outputs through 220 ? series resistors and external digital output buffers. power-down input the MAX12557 has two power modes that are con- trolled with a power-down digital input (pd). with pd low, the MAX12557 is in its normal operating mode. with pd high, the MAX12557 is in power-down mode. the power-down mode allows the MAX12557 to effi- ciently use power by transitioning to a low-power state when conversions are not required. additionally, the MAX12557 parallel output bus goes high-impedance in power-down mode, allowing other devices on the bus to be accessed. in power-down mode all internal circuits are off, the analog supply current reduces to less than 50?, and the digital supply current reduces to 1?. the following list shows the state of the analog inputs and digital out- puts in power-down mode. 1) inap/b, inan/b analog inputs are disconnected from the internal input amplifier (figure 3). 2) refout has approximately 17k ? to gnd. 3) refap/b, coma/b, refan/b enter a high-imped- ance state with respect to v dd and gnd, but there is an internal 4k ? resistor between refap/b and coma/b as well as an internal 4k ? resistor between refan/b and coma/b. 4) d0a?13a, d0b?13b, dora, and dorb enter a high-impedance state. 5) dav enters a high-impedance state. 6) clkp, clkn clock inputs enter a high-impedance state (figure 4). the wake-up time from power-down mode is dominated by the time required to charge the capacitors at ref_p, ref_n, and com_. in internal reference mode and buffered external reference mode the wake-up time is typically 10ms. when operating in the unbuffered exter- nal reference mode the wake-up time is dependent on the external reference drivers. dual, 65msps, 14-bit, if/baseband adc 20 ______________________________________________________________________________________ differential input voltage (lsb) two's-complement output code (lsb) -8189 +8191 +8189 -1 0 +1 -8191 0x2000 0x2001 0x2002 0x2003 0x1fff 0x1ffe 0x1ffd 0x3fff 0x0000 0x0001 2/3 x (v refp - v refn ) 2/3 x (v refp - v refn ) 1 lsb = 4/3 x (v refp - v refn ) / 16,384 figure 6. two?-complement transfer function (g/ t = 0) differential input voltage (lsb) gray output code (lsb) -8189 +8191 +8189 -1 0 +1 -8191 0x0000 0x0001 0x0003 0x0002 0x2000 0x2001 0x2003 0x1000 0x3000 0x3001 2/3 x (v refp - v refn ) 2/3 x (v refp - v refn ) 1 lsb = 4/3 x (v refp - v refn ) / 16,384 figure 7. gray-code transfer function (g/ t = 1)
MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 21 binary-to-gray code conversion 1) the most significant gray-code bit is the same as the most significant binary bit. 01 10 01 00 110 0 binary gray code 0 2) subsequent gray-code bits are found according to the following equation: d13 d7 d3 d0 gray x = binary x + binary x + 1 bit position 01 10 01 00 110 0 binary gray code 0 bit position gray 12 = binary 12 binary 13 gray 12 = 1 0 gray 12 = 1 1 3) repeat step 2 until complete: 01 10 01 00 110 0 binary gray code 0 bit position gray 11 = binary 11 binary 12 gray 11 = 1 1 gray 11 = 0 10 4) the final gray-code conversion is: 01 10 0100 1100 binary gray code 0 bit position 101 11 0 1 1010 gray-to-binary code conversion 1) the most significant binary bit is the same as the most significant gray-code bit. 2) subsequent binary bits are found according to the following equation: binary x = binary x+1 bit position binary 12 = binary 13 gray 12 binary 12 = 0 1 binary 12 = 1 3) repeat step 2 until complete: 4) the final binary conversion is: 01 0 0 1110 1010 binary gray code bit position 0 binary gray code 01 0 0 11 0 1 1010 binary 11 = binary 12 gray 11 binary 11 = 1 0 binary 11 = 1 gray x 0101 11 10 1010 binary gray code 0 bit position 1 01 0 1110 1010 binary gray code 0 bit position 11 01 1 1 0100 1100 ab y=ab 00 01 10 11 0 1 1 0 exclusive or truth table where is the exclusive or function (see truth t able below) and x is the bit position: + where is the exclusive or function (see truth t able below) and x is the bit position: + + + + + + + + + + + + + + + figure 8 shows the gray-to-binary and binary-to-gray code conversion in offset binary format. the output format of the MAX12557 is two's-complement binary, hence each msb of the two's-complement output code must be inserted to reflect true offset binary format. d11 11 11 11 11 10 11 10 d13 d7 d3 d0 d11 110 d13 d7 d3 d0 d11 11 01 d13 d7 d3 d0 d11 d13 d7 d3 d0 d11 d13 d7 d3 d0 d11 d13 d7 d3 d0 d11 d13 d7 d3 d0 d11 figure 8. binary-to-gray and gray-to-binary code conversion
MAX12557 applications information using transformer coupling in general, the MAX12557 provides better sfdr and thd with fully differential input signals than single- ended input drive, especially for input frequencies above 125mhz. in differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the adc inputs only requires half the signal swing compared to single-ended input mode. an rf transformer (figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12557 for optimum performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. the configuration of figure 9 is good for frequencies up to nyquist (f clk / 2). the circuit of figure 10 converts a single-ended input signal to fully differential just as figure 9. however, figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the nyquist frequency. a set of 75 ? and 113 ? termination resistors provide an equivalent 50 ? termination to the signal source. the second set of termination resistors connects to com_ providing the correct input common-mode voltage. two 0 ? resistors in series with the analog inputs allow high if input fre- quencies. these 0 ? resistors can be replaced with low- value resistors to limit the input bandwidth. single-ended ac-coupled input signal figure 11 shows an ac-coupled, single-ended input application. the max4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. dual, 65msps, 14-bit, if/baseband adc 22 ______________________________________________________________________________________ MAX12557 1 5 3 6 2 4 n.c. v in 0.1 f t1 minicircuits tt1-6 or t1-1t 24.9 ? 24.9 ? 5.6pf 5.6pf 0.1 f in_p com_ in_n figure 9. transformer-coupled input drive for input frequencies up to nyquist 1 5 3 6 2 4 n.c. v in 0.1 f t1 minicircuits adt1-1wt 5.6pf 5.6pf in_p com_ in_n *0 ? resistors can be replaced with low-value resistors to limit the input bandwidth. n.c. 1 5 3 6 2 4 n.c. t2 minicircuits adt1-1wt n.c. 75 ? 1% 75 ? 1% 113 ? 0.5% 113 ? 0.5% 0.1 f 0 ? * 0 ? * MAX12557 figure 10. transformer-coupled input drive for input frequencies beyond nyquist MAX12557 max4108 0.1 f 0.1 f 0 ? 5.6pf in_p com_ in_n 100 ? 100 ? v in 24.9 ? 24.9 ? 5.6pf figure 11. single-ended, ac-coupled input drive
buffered external reference drives multiple adcs the buffered external reference mode allows for more control over the MAX12557 reference voltage and allows multiple converters to use a common reference. the refin input impedance is >50m ? . figure 12 shows the max6029 precision 2.048v bandgap reference used as a common reference for multiple con- verters. the 2.048v output of the max6029 passes through a single-pole 10hz lp filter to the max4230. the max4250 buffers the 2.048v reference and pro- vides additional 10hz lp filtering before its output is applied to the refin input of the MAX12557. unbuffered external reference drives multiple adcs the unbuffered external reference mode allows for pre- cise control over the MAX12557 reference and allows multiple converters to use a common reference. connecting refin to gnd disables the internal refer- MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 23 max4230 0.1 f 1 f 5 2 3 4 1 1 5 2 refin v dd gnd 0.1 f 47 ? 3.3v 2.048v 16.2k ? refout 0.1 f ref_p ref_n com_ 0.1 f 0.1 f 0.1 f 2.2 f 0.1 f 3.3v 1.47k ? 300 f 6v note: one front-end reference circuit is capable of sourcing up to 15ma and sinking up to 30ma of output current. 10 f 0.1 f refin v dd gnd refout 0.1 f ref_p ref_n com_ 0.1 f 0.1 f 0.1 f 2.2 f 0.1 f 10 f 0.1 f MAX12557 max6029 (euk21) MAX12557 figure 12. external buffered (max4230) reference drive using a max6029 bandgap reference
MAX12557 ence, allowing ref_p, ref_n, and com_ to be driven directly by a set of external reference sources. figure 13 uses a max6029 precision 3.000v bandgap reference as a common reference for multiple convert- ers. a seven-component resistive divider chain follows the max6029 voltage reference. the 0.47? capacitor along this chain creates a 10hz lp filter. three max4230 amplifiers buffer taps along this resistor chain providing 2.413v, 1.647v, and 0.880v to the MAX12557 ref_p, ref_n, and com_ reference inputs. the feedback around the max4230 op amps provides additional 10hz lp filtering. reference volt- ages 2.413v and 0.880v set the full-scale analog input range for the converter to ?.022v (?v ref_p - v ref_n ] x 2/3). note that one single power supply for all active circuit components removes any concern regarding power- supply sequencing when powering up or down. grounding, bypassing, and board layout the MAX12557 requires high-speed board layout design techniques. refer to the MAX12557 ev kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, prefer- ably on the same side as the adc, using surface- dual, 65msps, 14-bit, if/baseband adc 24 ______________________________________________________________________________________ MAX12557 max4230 max6029 (euk30) 0.1 f 1 5 2 0.47 f 10 f 6v 47 ? 1.47k ? 2.413v 3v 4 1 3 330 f 6v max4230 10 f 6v 47 ? 1.47k ? 1.647v 4 1 3 330 f 6v max4230 10 f 6v 47 ? 1.47k ? 0.880v 4 1 3 330 f 6v ref_p ref_n com_ v dd gnd refin 3.3v 3.3v refout 0.1 f 0.1 f 0.1 f 10 f 0.1 f 2.2 f 0.1 f 20k ? 1% 20k ? 1% 20k ? 1% 20k ? 1% 20k ? 1% 52.3k ? 1% 52.3k ? 1% 0.1 f MAX12557 ref_p ref_n com_ v dd gnd refin refout 0.1 f 0.1 f 0.1 f 10 f 0.1 f 2.2 f 0.1 f 0.1 f figure 13. external unbuffered reference driving multiple adcs
mount devices for minimum inductance. bypass v dd to gnd with a 220? ceramic capacitor in parallel with at least one 10?, one 4.7?, and one 0.1? ceramic capacitor. bypass ov dd to gnd with a 220? ceramic capacitor in parallel with at least one 10?, one 4.7?, and one 0.1? ceramic capacitor. high-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins. multilayer boards with ample ground and power planes produce the highest level of signal integrity. all grounds and the exposed backside paddle of the MAX12557 must be connected to the same ground plane. the MAX12557 relies on the exposed backside paddle con- nection for a low-inductance ground connection. isolate the ground plane from any noisy digital system ground planes such as a dsp or output buffer ground. route high-speed digital signal traces away from the sensitive analog traces. keep all signal lines short and free of 90 turns. ensure that the differential, analog input network layout is symmetric and that all parasitic components are bal- anced equally. refer to the MAX12557 ev kit data sheet for an example of symmetric input layout. parameter definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for the MAX12557, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. inl deviations are measured at every step of the transfer function and the worst-case deviation is reported in the electrical characteristics table. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the MAX12557, dnl deviations are measured at every step of the transfer function and the worst-case deviation is reported in the electrical characteristics table. offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. ideally the midscale MAX12557 transition occurs at 0.5 lsb above mid- scale. the offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. ideally, the positive full- scale MAX12557 transition occurs at 1.5 lsbs below pos- itive full scale, and the negative full-scale transition occurs at 0.5 lsb above negative full scale. the gain error is the difference of the measured transition points minus the difference of the ideal transition points. small-signal noise floor (ssnf) ssnf is the integrated noise and distortion power in the nyquist band for small-signal inputs. the dc offset is excluded from this noise calculation. for this converter, a small signal is defined as a single tone with a -35dbfs amplitude. this parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise fig- ure of a digital receiver signal path. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr [max] = 6.02 n + 1.76 in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first six harmonics (hd2 through hd7), and the dc offset. snr = 20 x log (signal rms / noise rms ) signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 25
MAX12557 total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmon- ics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 7 are the amplitudes of the 2nd- through 7th-order harmonics (hd2 through hd7). spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -7dbfs. the inter- modulation products are as follows: 2nd-order intermodulation products (im2): f in1 + f in2 , f in2 - f in1 3rd-order intermodulation products (im3): 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 4th-order intermodulation products (im4): 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1, 2 x f in1 - 2 x f in2, 2 x f in1 + 2 x f in2, 2 x f in2 - 2 x f in1 5th-order intermodulation products (im5): 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1, 4 x f in1 - f in2, 4 x f in2 - f in1, 4 x f in1 + f in2, 4 x f in2 + f in1 3rd-order intermodulation (im3) im3 is the total power of the 3rd-order intermodulation product to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -7dbfs. the 3rd- order intermodulation products are 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 . aperture jitter figure 14 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 14). full-power bandwidth a large -0.2dbfs analog input signal is applied to an adc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as the full-power input bandwidth frequency. output noise (n out ) the output noise (n out ) parameter is similar to thermal plus quantization noise and is an indication of the con- verter? overall noise performance. no fundamental input tone is used to test for n out . in_p, in_n, and com_ are connected together and 1024k data points are collected. n out is computed by taking the rms value of the collected data points after the mean is removed. overdrive recovery time overdrive recovery time is the time required for the adc to recover from an input transient that exceeds the full-scale limits. the MAX12557 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by ?0%. the MAX12557 requires one clock cycle to recover from the overdrive condition. crosstalk coupling onto one channel being driven by a (-0.5dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. measurement includes all spurs resulting from both direct coupling and mixing components. thd vvvvvv v log = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 dual, 65msps, 14-bit, if/baseband adc 26 ______________________________________________________________________________________ t ad t aj t/h track hold hold clkn clkp analog input sampled d ata figure 14. t/h aperture timing
gain matching gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. the same input signal is applied to both channels and the maximum deviation in gain is report- ed (typically in db) as gain matching. offset matching like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two chan- nels are matched to each other. the same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %fsr) as offset matching. MAX12557 dual, 65msps, 14-bit, if/baseband adc ______________________________________________________________________________________ 27 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 refbp clkn v dd thin qfn top view v dd v dd ov dd dora d13a d12a d11a d10a d9a 52 53 d8a d7a div2 clkp v dd div4 v dd v dd ov dd v dd d1b d0b d3b d2b d4b d2a d1a d0a dav ov dd dorb d13b d12b d11b d10b 35 36 37 d9b d8b d7b exposed paddle (gnd) refbn gnd refan refap coma inbp inbn gnd gnd comb gnd gnd inan inap 48 d3a gnd 64 g/t 65 66 67 refout shref pd 68 refin 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 d5b d6b 34 33 49 50 d5a d4a 51 d6a 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 gnd 17 MAX12557 diffclk/seclk pin configuration
MAX12557 dual, 65msps, 14-bit, if/baseband adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 68l qfn thin.eps c 1 2 21-0142 package outline 68l thin qfn, 10x10x0.8mm c 2 2 21-0142 package outline 68l thin qfn, 10x10x0.8mm

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